The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology
The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage Digital System Test and Testable Design: Using ...
Are you interested in a specific from the book, like BIST or Boundary Scan , for a more detailed breakdown? Courses Syllabus – Monsoon 2024 - pgadmissions@iiit.ac.in The book by Zainalabedin Navabi (2010) is a
Random and deterministic test generation methods, plus sequential circuit test generation. Key Technical Coverage Are you interested in a
Scan architectures, RT-level scan design, and Boundary Scan (JTAG).
The text treats testing and testability as integral parts of the digital design process rather than afterthoughts.